İlk FPGA kartımı aldım (Basys3) ve test amaçlı küçük bir proje yazdım. 0'dan 9999'a kadar sayıyor sonra da en başa dönüyor. Asynchronous reset düğmesi de ekledim. Her modül ayrı dosyada ama paylaşmak amaçlı tek seferde paylaşıyorum. Doğru bir şekilde çalışıyor fakat timing hatası yaptım mı emin olamadım. İlk projem olduğu için sorayım dedim, bir bakarsanız sevinirim.
Kod:
`timescale 1ns / 1ps
module top(
input logic clk, btnC,
output logic [3:0] an,
output logic [6:0] seg
);
logic divided_clk;
logic [24:0] count;
logic [1:0] current;
logic clk0, clk1, clk2, clk3;
logic [3:0] num0, num1, num2, num3;
logic [3:0] num0_sync, num1_sync, num2_sync, num3_sync;
logic [16:0] mux_counter;
logic [0:6] driver0, driver1, driver2, driver3;
always_ff@(posedge clk)
begin
if (count == (25_000_000 - 1))
begin
count <= 0;
divided_clk <= ~divided_clk;
end
else
count <= count + 1;
end
always_ff@(posedge clk)
begin
num0_sync <= num0;
num1_sync <= num1;
num2_sync <= num2;
num3_sync <= num3;
end
always_ff@(posedge clk)
begin
mux_counter <= mux_counter + 1;
if (mux_counter == 0)
begin
current <= current + 1;
end
end
always_comb
begin
case(current)
0:
begin
an = 4'b1110;
seg = driver0;
end
1:
begin
an = 4'b1101;
seg = driver1;
end
2:
begin
an = 4'b1011;
seg = driver2;
end
3:
begin
an = 4'b0111;
seg = driver3;
end
default:
begin
an = 4'b1111;
seg = 7'b1111111;
end
endcase
end
count_module first(divided_clk, btnC, clk0, num0);
count_module second(clk0, btnC, clk1, num1);
count_module third(clk1, btnC, clk2, num2);
count_module fourth(clk2, btnC, clk3, num3);
driver first_driver(num0_sync, driver0);
driver second_driver(num1_sync, driver1);
driver third_driver(num2_sync, driver2);
driver fourth_driver(num3_sync, driver3);
endmodule
module count_module(
input logic clock, reset,
output logic done,
output logic[3:0] number
);
logic [3:0] current_number;
always_ff@(posedge clock or posedge reset)
begin
if(reset)
begin
current_number <= 0;
done <= 0;
end
else
if(current_number == 9)
begin
done <= 1;
current_number <= 0;
end
else
begin
current_number <= current_number + 1;
done <= 0;
end
end
assign number = current_number;
endmodule
module driver(input logic [3:0] num,
output logic [0:6] y
);
always_comb
begin
case(num)
0:
y = 7'b1000000;
1:
y = 7'b1111001;
2:
y = 7'b0100100;
3:
y = 7'b0110000;
4:
y = 7'b0011001;
5:
y = 7'b0010010;
6:
y = 7'b0000010;
7:
y = 7'b1111000;
8:
y = 7'b0000000;
9:
y = 7'b0010000;
default:
y = 7'b1111111;
endcase
end
endmodule