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What does GDDR5X memory technology bring to new Nvidia GeForce GTX 1080? Difference between GDDR5 and GDDR5X is explained. New memory bandwidth is shown in this presentation.
This video was recorded at U.S.A. Texas Austin Nvidia Global Presentation of GeForce GTX 1080 and GTX 1070. After the agreed NDA date we are making the record publicly available for all technology enthusiasts. There are great many details about new Nvidia Pascal architecture, new 16 nanometer production process, new drivers, software features and VR (Virtual Reality) in this series.
Nvidia GeForce GTX 1080 Review: NVIDIA GeForce GTX 1080 İncelemesi - Technopat (Turkish language)
Since the introduction of GDDR5 memory in 2009, NVIDIA's memory designers have been studying the possibilities for a next generation of memory signaling technology. GDDR5X is the culmination of that effort—the fastest and most advanced interface standard in history, achieving 10 Gbps transfer rates, or roughly 100 picoseconds (ps) between data bits. To put that speed of signaling in context, consider that light travels only about an inch in a 100 ps time interval. And the GDDR5X 10 circuit has less than half that time available to sample a bit as it arrives, or the data will be lost as the bus transitions to a new set of values.
To achieve this high speed of operation, a new 10 circuit architecture was needed, and it required a multi-year development project incorporating the latest advances in the fie Id. Every aspect of the new design was carefully crafted to meet the exacting standards of high frequency operation. Significant energy efficiency improvement was also attained through a combination of these circuit advances, the lower 1.35 V GDDR5X standard, and new process technologies, resulting in the same power consumption at 43% higher frequency.
in addition, the "channel" between the GPU die and the memory die had to be designed with great attention to detail. The speed of operation of the interface is determined solely by the speed of the weakest signal on the bus. Every signal between the GPU and memory die was carefully studied along its entire path out of the GPU, through the package, onto the board and over to the memory die, with attention to channel loss, crosstalk, and discontinuities that can degrade the signal.
Overall, the circuit and channel improvements described above not only enable GDDR5X at 10 Gbps, but also provide benefits for future products that use GDDR5 memory.
The following pictures illustrate some elements of the design, including the 10 circuit layout, and an extracted model of the path of one signal, highlighted in yellow, from the GPU (upper left) to DRAM pads (lower right) on the GeForce GTX 1080's new board channel design.
Engineering advances needed to make GDDR5X memory a reality on the GeForce GTX
1080.
The right image above is a long-term scope capture of one signal of the GDDR5X memory system in operation. Every bit sample (either 0 or 1 ora transition) is captured, and overtime, a history is built up that can be studied to check the margins of the system. The large and symmetrical data "eye" in the middle of each transition demonstrates a successful design, with good margin for data capture.
This video was recorded at U.S.A. Texas Austin Nvidia Global Presentation of GeForce GTX 1080 and GTX 1070. After the agreed NDA date we are making the record publicly available for all technology enthusiasts. There are great many details about new Nvidia Pascal architecture, new 16 nanometer production process, new drivers, software features and VR (Virtual Reality) in this series.
Nvidia GeForce GTX 1080 Review: NVIDIA GeForce GTX 1080 İncelemesi - Technopat (Turkish language)
Since the introduction of GDDR5 memory in 2009, NVIDIA's memory designers have been studying the possibilities for a next generation of memory signaling technology. GDDR5X is the culmination of that effort—the fastest and most advanced interface standard in history, achieving 10 Gbps transfer rates, or roughly 100 picoseconds (ps) between data bits. To put that speed of signaling in context, consider that light travels only about an inch in a 100 ps time interval. And the GDDR5X 10 circuit has less than half that time available to sample a bit as it arrives, or the data will be lost as the bus transitions to a new set of values.
To achieve this high speed of operation, a new 10 circuit architecture was needed, and it required a multi-year development project incorporating the latest advances in the fie Id. Every aspect of the new design was carefully crafted to meet the exacting standards of high frequency operation. Significant energy efficiency improvement was also attained through a combination of these circuit advances, the lower 1.35 V GDDR5X standard, and new process technologies, resulting in the same power consumption at 43% higher frequency.
in addition, the "channel" between the GPU die and the memory die had to be designed with great attention to detail. The speed of operation of the interface is determined solely by the speed of the weakest signal on the bus. Every signal between the GPU and memory die was carefully studied along its entire path out of the GPU, through the package, onto the board and over to the memory die, with attention to channel loss, crosstalk, and discontinuities that can degrade the signal.
Overall, the circuit and channel improvements described above not only enable GDDR5X at 10 Gbps, but also provide benefits for future products that use GDDR5 memory.
The following pictures illustrate some elements of the design, including the 10 circuit layout, and an extracted model of the path of one signal, highlighted in yellow, from the GPU (upper left) to DRAM pads (lower right) on the GeForce GTX 1080's new board channel design.
Engineering advances needed to make GDDR5X memory a reality on the GeForce GTX
1080.
The right image above is a long-term scope capture of one signal of the GDDR5X memory system in operation. Every bit sample (either 0 or 1 ora transition) is captured, and overtime, a history is built up that can be studied to check the margins of the system. The large and symmetrical data "eye" in the middle of each transition demonstrates a successful design, with good margin for data capture.
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